🚀 go-pugleaf

             _M_i_n_u_t_e_s _F_r_o_m _t_h_e _O_c_t_o_b_e_r _1_3 _V_L_S_I _F_o_r_u_m

_C_h_a_i_r_m_a_n: Martin Snelgrove
_S_e_c_r_e_t_a_r_y: Jonathan Rose


1.  _D_e_t_a_i_l_s

   - Meeting time moved to 4:00pm on thursdays,  and  to  the  EE
     conference room.


2.  _S_u_m_m_a_r_y__o_f__L_o_c_a_l__V_L_S_I__C_A_D__w_o_r_k

Each person attending the forum gave a short description  of  the
work  that they did as relating to VLSI.  This work is summarized
as follows:

2.1  _R_a_y_a_n__Z_a_c_h_a_r_i_a_s_s_e_n

   - Developing a lisp-based  computational  geometry  tool.   It
     allows  interactive input of geometrical shapes, and manipu-
     lation of those shapes.  The data is stored in the form of a
     Quad  tree,  for efficient storage and searching. It accepts
     the full subset of CIF as input as well.

   - program will do boolean operations of layers of  rectangles,
     which can be used to make a design rule checking system.

   - program can also be used to generate a  "MENU-Lay"  type  of
     automatic menu generation system.

   - also can be used as a graphics editor.

   - could also do interactive electrical rules checking.

   - Can add arbitrary lisp code to cells, making  them  intelli-
     gent  -  e.g.   make  a  driver  that  figures  out how much
     polysilicon/metal it has to drive, and then makes itself big
     enough to do it.


_N_o_t_e: Relating to Quad trees, a seminar is being  given  (through
the  department  of Computer Science) on thursay October 20th  at
11:00am in Room GB 248.  It is entitled "An Overview of  Quadtree
Research",  by  prof  Hanan  Samet, of the Department of Computer
Science, University of Maryland.

2.2  _J_o_n_a_t_h_a_n__R_o_s_e

   - recently written a program called  "cifca",  which  converts
     CIF  to  caesar  input  form.  It currently will convert any
     file output by caesar into CIF back into  caesar  form.   It










                              - 2 -


     breaks its teeth on some foreign CIF, and so needs some fix-
     ing.  It is useful for programs  that  change  caesar-output
     CIF  a little,  in the same form as caesar, and then need to
     be converted back to caesar to be viewed.

   - currently working on porting a graphics package  (rasterpac)
     to  the AED512 colour display/processor.  Will then add some
     features that make more use of the AED.

   - principle objective: specialized hardware for  VLSI  layout.
     (Ph.D.  Thesis)  Based  on  a  standard cell approach.  Will
     involve a parallel processor on some kind.  Intention is  to
     develop  parallel  architecture  and  algorithms to markedly
     speed up automatic partitioning, placement and routing.

2.3  _D_a_v_e__L_e_w_i_s

   - working on moving large portions of HUBNET  (a  local  local
     area  network)  to  gate  arrays.  Intention is to use MITEL
     gate arrays.

   - Brian Thomson (not present) is working on a circuit  extrac-
     ter for caesar-produced gate arrays.  This need only extract
     metal and poly connections given that the gate array  struc-
     ture is already known.

2.4  _L_a_r_r_y__P_h_i_l_p_s

   - also working on HUBNET  (Master's Thesis).

   - principle objective is automatic routing for gate arrays.

   - currently  designing  an  environment  for  testing  various
     automatic  routers: this involves writing a graphics package
     for the HP plotter, to facilitate  plotting  CIF  and  other
     layout represetations.

   - may use own layout represetation, more conducive to  routing
     - possibly the representation used by Brian Thomson.

2.5  _A_d_r_i_a_n__H_a_r_t_o_g

   - principle purpose is the chief engineer for  the  Microelec-
     tronics  Development  Centre, whose mandate is to design and
     produce gate arrays for outside customers. (notice the simi-
     larity to HUBNET)

   - intention is to purchase useable software towards this end

2.6  _C_a_t_h_y__M_c_Q_u_e_e_n

   - principle objective is  developing  design  tools  for  VLSI
     (Master's Thesis).










                              - 3 -


   - will be developing "smart cells" such  as  those  that  were
     described  above  under Rayan.  That is, cells that can both
     simulate and reconfigure themselves.

   - will investigate V-H trees, as a more  suitable  alternative
     to layout representation.

2.7  _J_a_r_o__P_r_i_s_t_u_p_a

   - working  on  a  multitude  of  simulators,  layout  editors,
     plotters and other things to be presented at the next Forum.

2.8  _A_l_e_x__S_h_u_b_a_t

   - principle objective is the design of  a  digital  multiplier
     using  DYNAMIC  CMOS.   Cider  Seminar  to  be  given later.
     (Master's Thesis)

2.9  _Z_a_h_i_r__P_a_r_p_i_a

   - principle objective is design of High  Voltage  IC  devices.
     (Ph.D. Thesis)

   - using the SUPREM process simulator


Submitted, October 18, 1983, by Jonathan Rose