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Article #3223Re: Mixing PIII processors with differing cache sizes
From: Jeremy
Date: Wed, 01 Jan 2003 00:00
Date: Wed, 01 Jan 2003 00:00
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2966 bytes
GrahamBanks wrote: > Intel's Processor Specification Update says: > > While there are no known issues associated with the mixing of processors > with differing cache sizes in a dual processor > system, and Intel has done nothing to specifically prevent such system > configurations from operating, Intel does not support > such configurations since there may be uncharacterized errata that exist. > In dual processor systems, all processors must be of > the same cache size. > > Is anyone aware of any issues with mixing processors with differing cache > sizes? Has anyone successfully done it? > > -- > Graham The cache available on each processor will be equal to the amount of the smaller cached proc. I think this statement was regarding Xeons...in which case you would be wasting alot of money for that unused cache. With non-Xeon P3s, different cache sizes can mean quite different procs with diff FSB speeds. For example, you definately don't want to mix 100MHz FSB and 133MHz FSB slot1s (which are 512k and 256k cache respectively). Really you should try to get identical steppings for SMP (look for someone selling a matched pair) to ensure they will play nicely together. Or at least check Intel's charts to ensure two different steppings are compatible. Jeremy __________________________________________________________________ Please remove your windows partition when replying by email
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: fdc9c,7c3fc51986e3bc17 X-Google-Attributes: gidfdc9c,public X-Google-Thread: 102b32,7c3fc51986e3bc17 X-Google-Attributes: gid102b32,public X-Google-Thread: 11196f,7c3fc51986e3bc17 X-Google-Attributes: gid11196f,public X-Google-Thread: 1113fa,7c3fc51986e3bc17 X-Google-Attributes: gid1113fa,public X-Google-Thread: f5f89,7c3fc51986e3bc17 X-Google-Attributes: gidf5f89,public X-Google-ArrivalTime: 2002-12-31 15:59:16 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!sn-xit-02!sn-xit-06!sn-xit-08!supernews.com!newsswitch.lcs.mit.edu!newsfeed.cwix.com!iad-peer.news.verio.net!news.verio.net!ord-read.news.verio.net.POSTED!not-for-mail From: Jeremy <jjs@yourwindowspartition.owc.net> Subject: Re: Mixing PIII processors with differing cache sizes Newsgroups: alt.comp.hardware,comp.os.linux.hardware,comp.sys.ibm.pc.hardware.systems,intel.microprocessors.pentium_iii,redhat.hardware.arch.intel Followup-To: alt.comp.hardware References: <ausrm8$qji$1@newsg2.svr.pol.co.uk> Lines: 36 User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Message-ID: <wcqQ9.28872$A%3.377753@ord-read.news.verio.net> Date: Wed, 01 Jan 2003 00:00:28 GMT NNTP-Posting-Host: 216.127.255.95 X-Complaints-To: abuse@verio.net X-Trace: ord-read.news.verio.net 1041379228 216.127.255.95 (Wed, 01 Jan 2003 00:00:28 GMT) NNTP-Posting-Date: Wed, 01 Jan 2003 00:00:28 GMT Organization: Verio