Thread View: alt.computer.consultants.ad
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Started by Grace Law
Wed, 26 Mar 1997 00:00
LOOKING FOR A CHIP/LAYOUT VERIFICATION ENGINEER!
Author: Grace Law
Date: Wed, 26 Mar 1997 00:00
Date: Wed, 26 Mar 1997 00:00
37 lines
2302 bytes
2302 bytes
Company: Software Engineering Solutions, Inc. Position: Chip/Layout Verification Engineer Date Posted: 3/26/97 You asked for it! A job as a Chip/Layout Verification Engineer in one of the hottest companies in the Silicon Valley. You will be doing Chip layout verification for Fiber Channel interface ASIC. DUTIES: Extraction of LSI test vectors Support for netlist changes during layout arising from logic or timing defects found Post-layout timing verification SKILLS: Verilog (required) Simulation test coding, gate level (required) Test vector extraction (required) LSI experience (strongly preferred) LSI Toolkit (strongly preferred) MOTIVE timing verification (preferred) Location: Cupertino When: ASAP! Salary: $60-$94/hr. Duration: 3+ months Call or send resumes to: Naomi Tran Software Engineering Solutions, Inc. 914 N. Rengstorff Ave. Mountain View, CA 94042 Voice: 415-969-0141 Fax: 415-969-0177 Email: tran@sesinc.com (text only)
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