Tristate Inverter

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1 total messages Started by Jacky Chen Loong Sang Thu, 27 Jan 2000 00:00

#145

Author: Jacky Chen Loong Sang
Date: Thu, 27 Jan 2000 00:00

18 lines
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Hello,
        Does anyone know what is HIGH IMPEDANCE meant in tristate
inverter when its Enable input is LOW.
        I use tristate inverter to select one of the few function blocks
in a time. I'm now simulating one of the function block with spice3 that
work together with magic VLSI design tool.When Enable is LOW, what
waveform will be shown in the output ?
        The resulted waveform that I got is ---when Enable is LOW, the
output waveform is follow the previous output.
        I'm not sure whether my circuit right or not. I've built the
tristate inverter as 2 pMOS above of 2 nMOS. One of the pMOS and nMOS
are connected to input, A, the other pMOS is connected to /Enable (
inverted input of Enable) and the other nMOS is connected to Enable.
        Am I using the correct method to select function?
        Thanks for your kindness to teach me.

Sincerely,
Jacky Chen

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