Article View: comp.arch.fpga
Article #22Re: SoC pheripheral Design Resouraces
From: Jussi Lähteenmäki
Date: Tue, 18 Feb 2003 07:38
Date: Tue, 18 Feb 2003 07:38
28 lines
2794 bytes
2794 bytes
In comp.lang.vhdl geeko <jibin@ushustech.com> wrote: All bus-protocols are easily described as state machines. If your peripheral is a simple slave, your only concern is pretty much whether you want to insert wait-states or not. I'd prefer the register-file approach, in which your peripheral is just a location in the memory space. You work with predefined delays (ie. how long it takes to read or write a certain location) which leads to fixed wait-states and eases the design (If I remember correctly AHB master can not insert wait states, so you don't have to worry about that). I know this sounded like a bunch of mambo jambo, but start simple and design a unit with only one n-bit register, make it read-only and work from there up. And keep it synchronous... regards, juza : I have a problem with the design of an SoC peripheral cell to be used in an : SoC with AHB interface .I am new to this area.Any resource or advices : regarding the design of an SoC peripheral : Thanks in Advance : Regards Geeko -- Juza
Technical Details
Message-ID:
<b2sntu$t3v$1@news.cc.tut.fi>Path:
arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!sn-xit-02!sn-xit-06!sn-xit-08!supernews.com!freenix!deine.net!uio.no!newsfeed1.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mailReferences:
<b2qi25$1efn70$1@ID-159027.news.dfncis.de>Show Full Headers
Complete Article Headers
X-Google-Language: ENGLISH,ASCII-7-bit
X-Google-Thread: 1151b2,4d8c7b9f65c148db
X-Google-Attributes: gid1151b2,public
X-Google-Thread: 1089ad,4d8c7b9f65c148db
X-Google-Attributes: gid1089ad,public
X-Google-Thread: fec08,4d8c7b9f65c148db
X-Google-Attributes: gidfec08,public
X-Google-Thread: 112e4c,4d8c7b9f65c148db
X-Google-Attributes: gid112e4c,public
X-Google-Thread: 109e85,4d8c7b9f65c148db
X-Google-Attributes: gid109e85,public
X-Google-Thread: 104c88,4d8c7b9f65c148db
X-Google-Attributes: gid104c88,public
X-Google-Thread: f57fe,4d8c7b9f65c148db
X-Google-Attributes: gidf57fe,public
X-Google-Thread: f736a,4d8c7b9f65c148db
X-Google-Attributes: gidf736a,public
X-Google-ArrivalTime: 2003-02-17 23:39:23 PST
Path: arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!sn-xit-02!sn-xit-06!sn-xit-08!supernews.com!freenix!deine.net!uio.no!newsfeed1.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail
From: Jussi Lähteenmäki <jusa@students.cc.tut.fi>
Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl,comp.lsi,comp.lsi.cad,fa.info-vlsi,fj.comp.lang.verilog,fj.comp.lang.vhdl
Subject: Re: SoC pheripheral Design Resouraces
Date: Tue, 18 Feb 2003 07:38:38 +0000 (UTC)
Organization: Tampere University of Technology
Lines: 28
Sender: Jussi Lähteenmäki <jusa@tutor.cc.tut.fi>
Message-ID: <b2sntu$t3v$1@news.cc.tut.fi>
References: <b2qi25$1efn70$1@ID-159027.news.dfncis.de>
NNTP-Posting-Host: tutor.cc.tut.fi
X-Trace: news.cc.tut.fi 1045553918 29823 130.230.10.24 (18 Feb 2003 07:38:38 GMT)
X-Complaints-To: abuse@tut.fi
NNTP-Posting-Date: Tue, 18 Feb 2003 07:38:38 +0000 (UTC)
User-Agent: tin/1.4.5-20010409 ("One More Nightmare") (UNIX) (OSF1/V4.0 (alpha))