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Article #24Re: SoC pheripheral Design
From: Rudolf Usselmann
Date: Tue, 18 Feb 2003 15:24
Date: Tue, 18 Feb 2003 15:24
40 lines
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3222 bytes
"geeko" <jibin@ushustech.com> wrote in message news:<b2spc6$1fgeh2$1@ID-159027.news.dfncis.de>... > Hi Jan > I am not so much worried about AHB interface any way it is a standard.I am > confused with the design of the core.The core will finally > become the part of an SoC which has ARM processor core .I want to get some > guidlines to the core design so as to make the core programmable by the ARM > processor.Any refrerence design or documents about a core design for an Soc Hmm, what kind of a core are you designing ? Perhaps you should take a look at www.opencores.org, there you will find many, many different IP cores. Perhaps doing some research on your own will answer your question. Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV ----- > "Jan De Ceuster" <Jan.DeCeuster@elis.rug.ac.be> wrote in message > news:3E50DFB4.BBFFE817@elis.rug.ac.be... > > > Hi all > > > I have a problem with the design of an SoC peripheral cell to be used in > an > > > SoC with AHB interface .I am new to this area.Any resource or advices > > > regarding the design of an SoC peripheral > > > > > > Thanks in Advance > > > Regards Geeko > > > > Geeko, what is exactly your problem? You're a bit vague here. > > For the AHB interface itself you should look into the AMBAv2.0 spec > > which is downloadable at the ARM website. Nothing is going to help you > > more than that spec because ARM did a good job in creating this > > document. > > > > Jan
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 1151b2,4d8c7b9f65c148db X-Google-Attributes: gid1151b2,public X-Google-Thread: 1089ad,4d8c7b9f65c148db X-Google-Attributes: gid1089ad,public X-Google-Thread: 104c88,4d8c7b9f65c148db X-Google-Attributes: gid104c88,public X-Google-Thread: 112e4c,4d8c7b9f65c148db X-Google-Attributes: gid112e4c,public X-Google-Thread: fec08,4d8c7b9f65c148db X-Google-Attributes: gidfec08,public X-Google-Thread: 109e85,4d8c7b9f65c148db X-Google-Attributes: gid109e85,public X-Google-Thread: f57fe,4d8c7b9f65c148db X-Google-Attributes: gidf57fe,public X-Google-Thread: f736a,4d8c7b9f65c148db X-Google-Attributes: gidf736a,public X-Google-ArrivalTime: 2003-02-18 07:24:16 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!postnews1.google.com!not-for-mail From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl,comp.lsi,comp.lsi.cad,fa.info-vlsi,fj.comp.lang.verilog,fj.comp.lang.vhdl Subject: Re: SoC pheripheral Design Date: 18 Feb 2003 07:24:16 -0800 Organization: http://groups.google.com/ Lines: 40 Message-ID: <d44097f5.0302180724.fb7d997@posting.google.com> References: <b2qi25$1efn70$1@ID-159027.news.dfncis.de> <3E50DFB4.BBFFE817@elis.rug.ac.be> <b2spc6$1fgeh2$1@ID-159027.news.dfncis.de> NNTP-Posting-Host: 203.121.131.36 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1045581856 29859 127.0.0.1 (18 Feb 2003 15:24:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 18 Feb 2003 15:24:16 GMT