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Article #25

Re: SoC pheripheral Design

#25
From: Jan De Ceuster
Date: Thu, 20 Feb 2003 08:32
47 lines
4119 bytes
> > Hi Jan
> > I am not so much worried about AHB interface any way it is a standard.I am
> > confused with the design of the core.The core will finally
> > become the part of an SoC which has ARM processor core .I want to get some
> > guidlines to the core design so as to make the core programmable  by the ARM
> > processor.Any refrerence design or documents about a core design for an Soc
> 
> Hmm, what kind of a core are you designing ?
> 
> Perhaps you should take a look at www.opencores.org, there
> you will find many, many different IP cores. Perhaps doing
> some research on your own will answer your question.
> 
> Regards,
> rudi

Huh, wierd I can't see your reply Geeko. Maybe because it's posted in
one of the other newsgroups? Oh well, I can see it in Rudi's reply.

So you want to create a peripheral that can be configured (to some
extend) by the ARM processor. That is quite easy to do. You're
peripheral will be addressed by the ARM with an unique address. Well
nothing stops you from using an addressrange. According to the ABH spec
an AHB peripheral occupies the memorymap in blocks of 1024 bytes (check
the spec because I'm not sure about this number). So when the peripheral
is activated you only need to check the lowest bits of the address. In
this way you can easily put data into some registers. This data can be
anything from setting the behaviour to parameters for some sort of
calculation. The software is responsible to put the correct data into
this register.

From software point of view it's just pointer accesses to certain
locations in memory. If your peripheral is located at base address
0x1000000 and it occupies 800 bytes then the memory range for that
peripheral is 0x1000000 to 0x1000319 or base + 0x0 to base + 0x319. And
the peripheral only checks the lowest bits so 0x0 to 0x319 (just ignor
the upper part of the address).

Mind that for the AHB there are some restrictions on the boundaries of
that 1024 bytes block (burst mode I think). Also try to limit the number
of real bus accesses. Writing 4 bytes on a 32 bit bus to address
0x1000000 is faster than writing the same to 0x1000001.

Hope this answers your questions?

kind regards,
Jan
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From: Jan De Ceuster <Jan.DeCeuster@elis.rug.ac.be>
Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl,comp.lsi,comp.lsi.cad,fa.info-vlsi,fj.comp.lang.verilog,fj.comp.lang.vhdl
Subject: Re: SoC pheripheral Design
Date: Thu, 20 Feb 2003 09:32:35 +0100
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