DFT , Design For Test HELPPPPP

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Article #41

#41

From: Djohn
Date: Tue, 01 Oct 2002 06:11

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2030 bytes

Hi all,
  I am now designing a Uart chip for study purposes. Now I am almost over
with my design and VHDL Coding .  I would like to integrate the DFT strategy
in the chip .

1)what are the different methods by which i can implement "Design for Test "
strategy in my chip.

2) I have a fair good knowledge of JTAG . So If I integrate a JTAG circuitry
in the chip (the tap controller , data registers  and instruction
registers), will it become  DFT compatible?

3) What exactly is BIST ? How is it implemented ? Any online  tutorials or
good links ...

4) What is ATPG ? how is it implemented? Any online  tutorials .......

5)Any other DFT strategies other than these.????

6) A comparison between these strategies? any links also welcome

thanks
Djohn

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From: "Djohn" <deepucjohn@yahoo.com>
Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,fj.comp.lang.vhdl
Subject: DFT , Design For Test  HELPPPPP
Date: Tue, 1 Oct 2002 11:41:22 +0530
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