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Article #42

Re: DFT , Design For Test HELPPPPP

#42
From: lee
Date: Thu, 03 Oct 2002 02:23
29 lines
2231 bytes
I've found the Altera SignalTap solution helpfull when I needed to
probe internal FPGA nodes.

lee

"Djohn" <deepucjohn@yahoo.com> wrote in message news:<anbej7$cg0fi$1@ID-159866.news.dfncis.de>...
> Hi all,
>   I am now designing a Uart chip for study purposes. Now I am almost over
> with my design and VHDL Coding .  I would like to integrate the DFT strategy
> in the chip .
> 
> 1)what are the different methods by which i can implement "Design for Test "
> strategy in my chip.
> 
> 2) I have a fair good knowledge of JTAG . So If I integrate a JTAG circuitry
> in the chip (the tap controller , data registers  and instruction
> registers), will it become  DFT compatible?
> 
> 3) What exactly is BIST ? How is it implemented ? Any online  tutorials or
> good links ...
> 
> 4) What is ATPG ? how is it implemented? Any online  tutorials .......
> 
> 5)Any other DFT strategies other than these.????
> 
> 6) A comparison between these strategies? any links also welcome
> 
> thanks
> Djohn
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From: tlee@post.com (lee)
Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,fj.comp.lang.vhdl
Subject: Re: DFT , Design For Test  HELPPPPP
Date: 2 Oct 2002 19:23:34 -0700
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