🚀 go-pugleaf

Hi Djohn,
the DFT strategies are used to allow testing components after production.
Sometimes the process is somehow faulty, so the silicon vendor must be able
to discard faulty pieces and investigate the reason.
One of the most used DFT strategies used for big IC (1 Mgates) is the scan
chain.
The design is synthesyzed using scanable flip-flops. They have one more
input called Test Input TI and a selector called Test Enable. When TE is
active (test mode), the FF uses TI as input, else the conventional input.
TI is connected to the ouput of another FF and all TE are connected
toghether.
Thus all the FFs are connected to make a long chain (the Scan Chain) and
selecting TE you can scan-in a special pattern and check the result
(pattern+result=Test Vectors).
For example: put the circuit in test mode (the scan chain is like a long
shift register); scan in a pattern; put it in normal mode and run 1 clock
cicle (the FF will now load new values according to the logic between them);
put the circuit in test mode; scan out the result (the result will depend on
the design itself).
You can simulate this test vectors and see the behaviour.
If the behaviour is OK you will release these Test Vectors to the silicon
vendor who will run them on the chips soon after the production. If the
outputs are as expected, the pieces will be delivered to the customer,
otherwise they will be trashed. The faulty results can be analyzed to find
where the circuit is faulty.
ATPG (Automatic Test Pattern Generator) is the tool which takes as an input
the circuit netlist, containing the scan chain, and generates the input
patterns (and I guess the result).
The vendor has a test machine where the components are placed (it's a sort
of pattern generator and logical anayzer togheter). The input patterns are
scaned-in the chip and the results are compared to the expected results.

BIST is another story. Built In Self Test is a test usually designed for
memories. Memories are likely to be faulty, so they need special test
algorithms to be run. The BIST block implements this specail algorithms
(March-...) and is usually provived togheter with the memory block. During
the normal mode BIST is quiet. Usually it is connected to the TAP. The TAP
should be designed so that you can issue an instruction to start the BIST
and check the result.
SO, if you have memories in your UART controller, you can implement it,
otherwise there's no point.
But I suppose if you had had a memory, you would have known about the BIST.

Thats all.
I am a HW designer from Italy and work for Ericsson, I'm 32 and my
experience is not so big. What do you do ? Student ?
Well, I hope I clarified you doubths.

Regards
Alessandro