🚀 go-pugleaf

mash@mips.com (John Mashey) writes:

>Age: number of years since first implementation sold in this family
>(or first thing of which this is binary compatible with)
>3a: # instruction sizes
>3b: maximum instruction size in bytes
>3c: number of distinct addressing modes for accessing data (not jumps)>
>3d: indirect addressing: 0: no, 1: yes
>4a: load/store combined with arithmetic: 0: no, 1:yes
>4b: maximum number of memory operands
>5a: unaligned addressing of memory references allowed in load/store,
>	without specific instructions
>	0: no never (MIPS, SPARC, etc)
>	1: sometimes (as in RS/6000)
>	2: just about any time
>5b: maximum number of MMU uses for data operands in an instruction
>6a: number of bits for integer register specifier
>6b: number of bits for 64-bit or more FP register specifier,
>	distinct from integer registers

You might add ARM to the list

CPU	Age	3a 3b 3c 3d	4a 4b 5a 5b	6a 6b	# ODD
RULE	<6	=1 =4 <5 =0	=0 =1 <2 =1	>4 >3
-------------------------------------------------------------------------
	6+ (7?)	 1  4 13+ 0      0  1? 0  1? 	 4+ 0+  4	ARM

Notes:

There are actually 4 bits that specify addressing mode, but
four of the 16 modes have the same effect. This is due to a very
orthogonal specification.

The (?) in 4b and 5b are due to the load/store multiple register
instructions, which use one memory access per register.

There are no FP unit on the chip, thus no specific FP registers. There
has been an announcement of an FPU to appear this year, but I don't
know anything about it.

I'm not certain about the age, but it was, I think, the first
commercially available RISC processor.

	Torben Mogensen (torbenm@diku.dk)