🚀 go-pugleaf

In comp.arch, andrey@cco.caltech.edu (Andre T. Yew) writes:

> 	About a week ago, in a class here at Caltech, the lecturer
> mentioned the idea of microprocessor density in terms of
> transistors and contacts.  He gave what he considered to be
> a dense layout in terms of area -- about 1 transistor or
> contact per 50 square lambda (lambda = 2 um, SCMOS) -- and
> showed several commercial processors...
> ...I'd just like to sat that I'm confused over why you seem to
> say 2.8 Mtransistors on an 11x11 mm^2, presumably, die is
> an impressive count.  If we apply the rule, an 11x11 die should
> yield about 26.9 million transistors, and given that there are
> generally a little more than two contacts per transistor, the
> 601 has about 9/27 = 33% of its expected yield...
>    ...The Mosaic C is a Caltech-designed processor that's
> meant for Caltech's multiprocessing machines.  I guess he
> had to throw that in to show that people could still get
> relatively dense layouts with million-transistor chips.  He
> said that one reason the Mosaic C is so dense is because
> it's mostly memory (I think more than 80% of its transistors
> is memory) and its memory was laid out by an immensely
> talented person... 

Well, when I want to measure my chip's density against someone else's, the
first thing I do is subtract the RAM and the area used by it from both
die. This is because it *doesn't* take an "immensely talented person" to
lay out a RAM cell that is obscenely dense compared to your metric. Without
trying hard I can get 6 transistors and 5 contacts (counting the shared ones
as half) in 150 square lambda (I'm assuming lambda = gate length). This is
a lambda/fet-or-contact of 13.6! If the RAM covers half of the die and the rest
is empty silicon, I can still get a score of 27!

So a raw fets-per-unit-area metric merely is a measure of how much of the 
die is covered with RAM, and the incremental performance per additional RAM
FET is probably lower than anything else on the die (such as, say, FETS in the
ALU or I-decode). 

On the other hand, well-crafted data paths and some standard-cell blocks can
concievably meet your metric. The PA7100 FP multiply unit achieves about 30 
(assuming 2 contacts per FET).

But a whole-die metric is really measuring the composition efficiency, since
a lot of die area goes to the power and interconnect area, as well as I/O 
ring. This area would be doing good to be within 10X of your standard.

I could think of a lot of interesting design metrics. How about

(SPECs * lambda) / non-RAM transistors

or

(SPECs * lambda) / non-RAM die area?

Note that we'd still have to excise the cache RAM, since on-board caches 
would generally lose to external-cache designs.

Either that or I couldn't play...;-)

Also note that an i8080 might still look pretty good...

Bob (PA7100 vet) Miller rhm@hpfirhm.FC.HP.COM