🚀 go-pugleaf

mhjohnso@oracle.com (Mark H. Johnson) writes:

> [Direct-mapped caches may have excellent mean performance but also have 
> large standard deviation.]

>The number of locations that generates the "cache clashes" that produce the 
>large increase in miss rates is often quite small.  (We measured this
>on Prime 50 series machines some time ago.  I assume programs still look
>about the same at this level.)  One idea we explored was that of asymetric
>caches.  Use a very large, direct-mapped cache for maximum cache size and 
>getting a large working set in cache, and add a small, fully or nearly fully
>associative cache in parallel as an "asymetric, sort of two-way set 
>associative cache".  This second set could be on-chip.  Simulations 
>suggested significant gains from this approach.

Sounds like victim caches - Jouppi claims very similar results:

%T Improving direct-mapped cache performance by the addition of small
fully-associative cache and prefetch buffers
%A Norman P. Jouppi
%J Proc 17th Symp Comp Arch, Seattle
%J SIGARCH News
%V 18
%N 2
%D June 1990
%P 364-373
%X small "victim caches" (1-5 entries) give significant speedup 

Does any commercial processor implement victim caches?  Why not?

-Urs

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Urs Hoelzle                                              urs@cs.stanford.EDU
Computer Systems Laboratory, CIS 57, Stanford University, Stanford, CA 94305