Article View: comp.arch
Article #10472Re: RISC vs. CISC -- SPECmarks
From: peter da silva
Date: Fri, 26 Apr 1991 21:05
Date: Fri, 26 Apr 1991 21:05
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In article <1991Apr26.073829.4625@kithrup.COM>, sef@kithrup.COM (Sean Eric Fagan) writes: > Or don't you realize you can only access one memory location at a time? > (Well, not completely true, but true enough.) Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to memory subsystems. How about multiported memory, or even banked memory? Multiple data and address busses? Who knows, but memory subsystems are the current bottleneck and something's gotta give. -- Peter da Silva. `-_-' peter@ferranti.com +1 713 274 5180. 'U` "Have you hugged your wolf today?"
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!rice!uupsi!ficc!peter From: peter@ficc.ferranti.com (peter da silva) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <TH_A6-F@xds13.ferranti.com> Date: 26 Apr 91 21:05:42 GMT References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr26.073829.4625@kithrup.COM> Organization: Ferranti International Controls Corporation Lines: 11