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Article #10473Re: RISC vs. CISC -- SPECmarks
From: Preston Briggs
Date: Sat, 27 Apr 1991 01:26
Date: Sat, 27 Apr 1991 01:26
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sef@kithrup.COM (Sean Eric Fagan) writes: >> Or don't you realize you can only access one memory location at a time? >> (Well, not completely true, but true enough.) and peter@ficc.ferranti.com (peter da silva) writes: >Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to >memory subsystems. How about multiported memory, or even banked memory? >Multiple data and address busses? Who knows, but memory subsystems are the >current bottleneck and something's gotta give. Well, you _could_ rediscover the Connection Machine. Preston Briggs
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!van-bc!ubc-cs!uw-beaver!rice!ariel.rice.edu!preston From: preston@ariel.rice.edu (Preston Briggs) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <1991Apr27.012655.6508@rice.edu> Date: 27 Apr 91 01:26:55 GMT References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr26.073829.4625@kithrup.COM> <TH_A6-F@xds13.ferranti.com> Sender: news@rice.edu (News) Organization: Rice University, Houston Lines: 15