🚀 go-pugleaf

In article <3423@charon.cwi.nl> dik@cwi.nl (Dik T. Winter) writes:
>In article <11412@mentor.cc.purdue.edu> hrubin@pop.stat.purdue.edu (Herman Rubin) writes:
> > The CYBER 205/ETA 10 is a vector pipeline machine, with the most versatile

>And now consider what occurs on a page fault in the middle of an instruction!
>A single vector instruction can create over 45 page faults.  Still worse if
>you only run out of the (16) associative registers used to cache page table
>entries (half page faults?).

>dik t. winter, cwi, amsterdam, nederland
>dik@cwi.nl

While the machine had its faults :-) the above is not one of them.
Vector instructions were continuable with no problems (all the necessary
state was saved, and in a reasonable length of time.)  The fact that one
instruction could riffle through a lot of pages is in no way
different than the fact that a scalar machine can riffle through
a lot of pages in a loop.

The fact that 16 AR's are not enough, is an amusing criticism.  True, but
what superscalar machine of today can map 16*64KW*8Bytes/Word  = 8 MegaBytes
in its TLB?  The ETA-10 had even bigger large pages...

PROPHECY:  One of these days, a single-chip microprocessor will have vector
instructions, and then the advantages and disadvantages of various
architectural decisions will be discovered all over again.

  Hugh LaMaster, M/S 233-9,  UUCP:                ames!lamaster
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