🚀 go-pugleaf

I'm posting this for a friend who was having trouble posting it at
his site.  Please don't send replies to me; post your reply or send
email to the address:
	gary@clipper.ingr.com


     O o
      X
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The other day I had a short discussion about 3 address verses 2
address architectures. The discussion went something like this.

Me> What do you think about 3 address architectures.

Him> I think they are a bad idea if you have a small number of
registers because they increase register pressure.

Me> That's not true.  For every 2 address sequence there is an
equivalent 3 address sequence. You simply use the destination
address of the two address instructions as both a source and
the destination address. Hence the sequences are equivalent in
register usage. Furthermore a 3 address sequence would allow
removal of any register-to-register copies required to preserve
the value of the the destination register. Hence the sequence is
tighter.

Him> Yeah, I see your point. But, I'd guess that the real
difference is still just in the noise. This is one of those
religious issues that everyone believes in but nobody has
proved. You don't have any hard performance numbers to back you
up do you?

Me> No.

What all this boils down to is the question does anybody out
there have any hard numbers on this? If so, what are they and
how/where did you get them.  If your mail bounces please post
the information. I will post a summary to the net.  Please no
SWAGs or back of the envelope calculations on this. I can make
as wild a guess as the next guy.

 *-------------------------*
 | Gary Oblock             | I apologize to those few people
 | Intergraph Corp.        | who saw this posting before. The
 | Advanced Processor Div. | news software didn't let it out
 | 2400 Geng Road          | to the real world. 
 | Palo Alto, CA 94303     |
 | (415)494-8800           |
 | gary@clipper.ingr.com   |
 *-------------------------*

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