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Article #10547Re: RISC vs. CISC -- SPECmarks
From: John D. McCalpin
Date: Thu, 02 May 1991 13:59
Date: Thu, 02 May 1991 13:59
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>On 2 May 91 01:54:10 GMT, lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) said: Hugh> PROPHECY: One of these days, a single-chip microprocessor will Hugh> have vector instructions, and then the advantages and Hugh> disadvantages of various architectural decisions will be Hugh> discovered all over again. I don't see much benefit to explicit vector instructions compared to tight loops with zero cycle branches (like the RS/6000). They sure can eat up a lot of silicon space, though.... The big problem is that the memory bandwidth required for vector FP is expensive and is not likely to contribute substantially to the non-FP performance. Without adequate memory bandwidth, there is not really any need for vector instructions, since the cpu is idle (waiting for cache refills) for plenty of time to do loop control.... -- John D. McCalpin mccalpin@perelandra.cms.udel.edu Assistant Professor mccalpin@brahms.udel.edu College of Marine Studies, U. Del. J.MCCALPIN/OMNET
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!batcomputer!cornell!rochester!udel!nigel.ee.udel.edu!mccalpin From: mccalpin@perelandra.cms.udel.edu (John D. McCalpin) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <MCCALPIN.91May2095930@pereland.cms.udel.edu> Date: 2 May 91 13:59:30 GMT References: <TH_A6-F@xds13.ferranti.com> <11412@mentor.cc.purdue.edu> <3423@charon.cwi.nl> <1991May2.015410.1470@news.arc.nasa.gov> Sender: usenet@ee.udel.edu Organization: College of Marine Studies, U. Del. Lines: 20 Nntp-Posting-Host: perelandra.cms.udel.edu In-reply-to: lamaster@pioneer.arc.nasa.gov's message of 2 May 91 01:54:10 GMT