🚀 go-pugleaf

In article <1991May8.155455.14491@midway.uchicago.edu> rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) writes:
>Andrew Glew, of Intel, writes
>>    So: why not combine vector memory access instructions that convey
>>access pattern, with scalar computational operations?
>
>Yes, yes, my point exactly.  Please do it!  I'll take 10.  
>In fact, I think a fruitful area for extending the current
>architectures is in a more general model for pre-loading
>the cache.  Doing pre-loads by constant strides rather
>than by contiguous lines would already be a big
>performance boost, but I could also imagine more
>general solutions, where you gave the memory subsystem a 
>vector of addresses which specified the pre-load pattern.
>

It just so happens we have done some preliminary work in prefetching data
into vector caches. The initial results seem quite encouraging. If you
are interested the references are:

J. W. C. Fu and J. H. Patel, "Data Prefetching Strategies for Vector
Cache Memories," 5th. Int'l Parallel Processing Symp., May 1991

J. W. C. Fu and J. H. Patel, "Data Prefetching in Multiprocessor
Vector Cache Memories," Proc. of 18th. Int'l Symp. on Computer    
Architecture, May 1991.


John Fu
Center for Reliable and High Performance Computing
University of Illinois at Urbana-Champaign
fu@crhc.uiuc.edu