Article View: comp.arch
Article #10721Re: Vector vs Cache/Superscalar
From: R. Kym Horsell
Date: Wed, 08 May 1991 19:12
Date: Wed, 08 May 1991 19:12
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In article <1991May8.155455.14491@midway.uchicago.edu> rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) writes: >Andrew Glew, of Intel, writes >In fact, I think a fruitful area for extending the current >architectures is in a more general model for pre-loading >the cache. Doing pre-loads by constant strides rather >than by contiguous lines would already be a big >performance boost, but I could also imagine more >general solutions, where you gave the memory subsystem a >vector of addresses which specified the pre-load pattern. > >I'm just a user though. I'm not at all clear how hard these >things would be to implement in hardware. The best place to preload the cache is in the compiler. :-) -kym
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!sarah!bingnews!kym From: kym@bingvaxu.cc.binghamton.edu (R. Kym Horsell) Subject: Re: Vector vs Cache/Superscalar Message-ID: <1991May8.191202.1788@bingvaxu.cc.binghamton.edu> Organization: State University of New York at Binghamton References: <11921@mentor.cc.purdue.edu> <GLEW.91May7172546@pdx007.intel.com> <1991May8.155455.14491@midway.uchicago.edu> Date: Wed, 8 May 1991 19:12:02 GMT