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Article #10759Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
From: Thomas Ruf
Date: Mon, 21 Dec 1992 21:16
Date: Mon, 21 Dec 1992 21:16
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mike@cbl.umd.edu (Michael Santangelo) writes: >So this theoretical EISA SCSI controller and this theoretical EISA FDDI >controller could both be doing DMA writes to main memory (interleaving their >accesses I assume)? Since PC's do not have multiport memory, I assume >the EISA subsystem would itself (on behalf of BOTH of these controllers) have >full control over the memory during the dual transfers, starving out the CPU? On EISA, the CPU(s) is (are) considered to be one of the potential bus masters, therefore the CPU(s) will get a fair share of the available bandwith. On MicroChannel, the CPU is usually the lowest priority bus master, therefore the peripherals "win" over the CPU. And, BTW: the above mentioned controllers are not theoretical only. -- Thomas Ruf tom@rsp.de Schneider & Koch GmbH
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Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!Germany.EU.net!rsp!tom From: tom@rsp.UUCP (Thomas Ruf) Newsgroups: comp.arch,comp.arch.storage Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus) Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO Message-ID: <1083@rsp.UUCP> Date: 21 Dec 92 21:16:34 GMT References: <1gntdfINNu7@cbl.umd.edu> <1992Dec16.211712.13142@twisto.eng.hou.compaq.com> <1992Dec17.153141.3926@urbana.mcd.mot.com> <1992Dec17.191131.17701@twisto.eng.hou.compaq.com> <1gul5nINN7ln@cbl.umd.edu> Organization: RSP Datensysteme, W-Germany Lines: 16