Article View: comp.arch
Article #10779Re: question about DMA devices
From: Jan Vorbrueggen
Date: Tue, 22 Dec 1992 18:33
Date: Tue, 22 Dec 1992 18:33
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In article <1992Dec18.175402.27841@hubcap.clemson.edu> dfk@wildcat.dartmouth.edu (David Kotz) writes: I have a question about DMA devices, specifically for networks and disks. Do you know if it is possible (and if so, common) for a DMA device to support scatter/gather? In particular, I'm trying to model a multiprocessor interconnect network interface, and it would be very helpful if I could avoid packetization by specifying the addresses and lengths of my message header and message body, for the network DMA to pick up. I'm guessing that this is not usually an option. Also, in a disk interface, can it read in a whole track but scatter the blocks to different locations in memory? I'm guessing that this kind of thing is more common. Well, as a historical perpective on this subject, consider what the I/O adapters of the Vax11/780 (ca. 1978?) did/do: They (Unibus and Massbus adapters) had a set of socalled mapping registers. These mapped an offset in an I/O transaction into the appropriate _physical_ address. A set of system routines was provided for drivers to load the mapping registers from the page table of a process (or system space) with the required data. (I think there are seperate routines to make sure the page tables contain valid entries in the relevant page range, which is especially important for I/O directly to/from user space. I do know there was an optimization for reads which didn't bother to page in pages from backing store which were going to be overwritten shortly by a read it just substituted a page from the free list and marked the page table entry as dirty.) A number of smaller Vaxen (only the uVaxI? or also the 725/730?) didn't have these and in general had to do I/O a page at a time...probably still slightly faster than a PC/XT :). A later adapter, the one for the CI (computer interconnect, four cables running at 70Mbit/s each) went even further: It reads I/O request packets from system virtual memory, containing pointers to buffers in virtual memory (I think user space buffers are double mapped into system space), and reads the page tables itself in order to determine physical addresses. Sort of like a closely coupled multiprocessor with one processor dedicated to I/O. (The rumour was that for the 750, the CI adapter was actually the faster CPU...) So this is quite an old trick, and not really that difficult to do. I would assume that current Unix/workstation systems do something similar. Jan
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!Germany.EU.net!news.uni-bielefeld.de!rz.ruhr-uni-bochum.de!jan From: jan@pallas.neuroinformatik.ruhr-uni-bochum.de (Jan Vorbrueggen) Subject: Re: question about DMA devices Message-ID: <JAN.92Dec22183354@pallas.neuroinformatik.ruhr-uni-bochum.de> Followup-To: comp.arch Organization: Inst. f. Neuroinformatik, Ruhr-Universitaet Bochum, FRG References: <1992Dec18.175402.27841@hubcap.clemson.edu> Date: 22 Dec 92 18:33:54 Lines: 45