Article View: comp.arch
Article #10822Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
From: william E Davidsen
Date: Wed, 23 Dec 1992 19:21
Date: Wed, 23 Dec 1992 19:21
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1741 bytes
In article <1gul5nINN7ln@cbl.umd.edu>, mike@cbl.umd.edu (Michael Santangelo) writes:
| So this theoretical EISA SCSI controller and this theoretical EISA FDDI
| controller could both be doing DMA writes to main memory (interleaving their
| accesses I assume)? Since PC's do not have multiport memory, I assume
| the EISA subsystem would itself (on behalf of BOTH of these controllers) have
| full control over the memory during the dual transfers, starving out the CPU?
a) these are shipping, not theoretical
b) every memory system has a limit to bandwidth, after which you make
either i/o or cpu wait. Most people find better total throughput when
they make the cpu wait. A quick calculation of the bandwidth of the bus
and any remotely plausible i/o system will tell you the cpu doesn't wait
long.
--
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
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Path: arc1-ca.pugleaf.net!sparky!uunet!crdgw1!rdsunx.crd.ge.com!ariel!davidsen From: davidsen@ariel.crd.GE.COM (william E Davidsen) Newsgroups: comp.arch,comp.arch.storage Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus) Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO Message-ID: <1992Dec23.192154.17137@crd.ge.com> Date: 23 Dec 92 19:21:54 GMT References: <1gntdfINNu7@cbl.umd.edu> <1992Dec16.211712.13142@twisto.eng.hou.compaq.com> <1992Dec17.153141.3926@urbana.mcd.mot.com> <1992Dec17.191131.17701@twisto.eng.hou.compaq.com> <1gul5nINN7ln@cbl.umd.edu> Sender: usenet@crd.ge.com (Required for NNTP) Reply-To: davidsen@crd.ge.com (bill davidsen) Organization: GE Corporate R&D Center, Schenectady NY Lines: 19 Nntp-Posting-Host: ariel.crd.ge.com