🚀 go-pugleaf

  This whole thing reminds me of 1950s mainframe design ala GE. The
heart of the system was the memory controller, and CPUs connected to the
memory controller(s), as did the i/o controller(s) (IOC). Off the i/o
controllers were the peripheral controllers (MPC - microprogrammed
controllers), and off those were the actual devices. With bandwidth
appropriately higher as you got closer to the memory.

  You had eight port memory controllers which could talk to any mix of
1-7 CPUs and 1-7 IOCs. If memory bandwidth became a problem you split
the memory between more memory controllers. If you ran out of i/o you
split devices between MPCs, or MPCs between IOCs. All datapaths to
memory were 72 bits, I *think* the IOC to MPC was 36, but I could be
wrong.

  Now a limit of 8 anythings isn't going to suffice in all cases today
(and didn't then), but the idea of hierarchical bandwidth is hardly new,
since these machines were shipping in the late 50s.

  One interesting artifact of this design is that cache may be on the
CPU *or* on the memory controller. Putting it on the controller
certainly eases problems of consistency, assuming you can resolve timing
problem having the cache off the CPU.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
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