🚀 go-pugleaf

Greetings:

I'm looking for any papers, documents or textbooks which are concerning
about the insturction-set layer parallelism. As far as I know, there
are many parallelisms can be pursued in the computing systems:

        . algorithm layer
        . environment layer
        . language and compiler layer
        . OS and library layer
        . instruction-set layer
        . hardware layer

It's my impression that most of current parallel system implementations
are mainly focused on hardware layer. I wonder whether instruction-set
layer parallelism is worth to explore. Current CISC/RISC processors
seem don't consider implementing any instructions which support the
concurrent execution (except floating-point operations). Although
some processors (such as Inmos's Transputer series) also include
the inter-processor communication instructions, I doubt this is the
only way to obtain the instrcution level parallelism.

The vector processors are good enough for array operations but are
criticized for most of the general-purpose programs are hard (if not
impossible) to transform into vector forms. So you can find that
additional vector processors are attached in TMC's CM-5 nodes.

MIT's dataflow machines seems be the only one computation model that can
support instruction level parallelism. Other High-Level-Language (HLL)
machines might be the another candidate, I'm not sure.

Superpipeline and superscalar, however, are not my interesting.

Please forward your direction to me.

Thanks,

Yin-Chih Lin    lycmit@x1sun6.ccl.itri.org.tw

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Yin-Chih Lin                   Industrial Technology Research Institute (ITRI)
Design Eng.                    Computer & Communication Research Labs.  (CCL)
lycmit@x1sun6.ccl.itri.org.tw  Microcomputer System Department X100
Tel: 886-35-917331             14 Bldg, 195 Chung Hsing Rd., Section 4
Fax: 886-35-917503             Chutung, Hsinchu 31015
                               Taiwan, R.O.C.