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Article #11118

Re: Relatively long cycle time in 486 LOOP instruction

#11118
From: Eliot Moss
Date: Thu, 17 Dec 1992 12:31
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1590 bytes
A guess as to why a decrement-and-branch instruction might take longer than
you expect is that if the processor is pipelined, they may stall instruction
issue until this instruction has resolved whether or not it is going to
branch. I don't know the instruction set in detail, but if these are
instructions where the branch target is in a register or computed (i.e., not
absolute in the instruction, or PC relative), you can also lose cycles in
getting the branch target fetched.
--

J. Eliot B. Moss, Associate Professor	Visiting Associate Professor
Department of Computer Science		School of Computer Science
Lederle Graduate Research Center	Carnegie Mellon University
University of Massachusetts		5000 Forbes Avenue
Amherst, MA  01003			Pittsburgh, PA  15213-3891
(413) 545-4206, 545-1249 (fax)		(412) 268-6767, 681-5739 (fax)
Moss@cs.umass.edu			Moss@cs.cmu.edu
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From: moss@cs.cmu.edu (Eliot Moss)
Newsgroups: comp.arch
Subject: Re: Relatively long cycle time in 486 LOOP instruction
Message-ID: <MOSS.92Dec17073124@CRAFTY.cs.cmu.edu>
Date: 17 Dec 92 12:31:24 GMT
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