DEC Alpha architecture issues

Article View: comp.arch

Article #11219

#11219

From: Keith Scidmore
Date: Wed, 18 Nov 1992 17:24

16 lines
1506 bytes

1. The DEC Alpha includes a conditional move instruction that they claim
   can be used to avoid using branches and the associated branch penalties.
   I'm trying to evaluate the usefulness of this feature.  Can someone tell
   me where I might find articles that discuss this or raw data that can be
   used to calculate the advantages of such an instruction.  I'm not into
   compilers, and I need to know what kinds of situations an optimizing
   compiler could make use of this instruction.  Is it even practical?  Are
   there any compiler writers out there with opinions on this?

2. The Alpha architecture also includes a feature they call PALcode that
   allows the chip to have a sort of rom-bios.  Why is it useful to have
   this feature?  Supposedly Operating systems can make use of this for
   the implementation of certain system calls.

3. Cray has annouced intention to build a 300 Teraflop machine based on the
   alpha.  What is the word for 1000 teraflops?

Technical Details

Message-ID: <1992Nov18.112407.2518@doug.cae.wisc.edu>

Path:

arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!sgiblab!zaphod.mps.ohio-state.edu!caen!umeecs!umn.edu!doug.cae.wisc.edu!keiths

Show Full Headers

Complete Article Headers

Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!sgiblab!zaphod.mps.ohio-state.edu!caen!umeecs!umn.edu!doug.cae.wisc.edu!keiths
From: keiths@cae.wisc.edu (Keith Scidmore)
Subject: DEC Alpha architecture issues
Organization: College of Engineering, Univ. of Wisconsin--Madison
Date: 18 Nov 92 11:24:06 CST
Message-ID: <1992Nov18.112407.2518@doug.cae.wisc.edu>
Summary: conditional moves, PALcode, 1000 Teraflops=?
Keywords: alpha architecture
Sender: Keith R. Scidmore
Lines: 21