🚀 go-pugleaf

woodacre@mips.com (Michael Woodacre) writes:
	[ in reference to PALcode ]
>Can you explain how this is different from kernel code with interrupts
>disabled on any other risc processor?

Think of it as a supervisor state. This state doesn't just have
interrupts disabled:  it also has direct access to a large variety of
implementation-specific internal registers. For example, TLB reloads
are done by PALcode, whereas the "normal" code in the OS need only
know architectural things (things that remain constant across
implementations). 

Also, PALcode can be entered from user state - you don't need to do a
system call, with its heavy-duty state-change overheads.
-- 
Don		D.C.Lindsay	Carnegie Mellon Computer Science