Article View: comp.arch
Article #11449Re: ACE (Was Re: Will NeXT survive? Grow with the times?)
From: Vernon Schryver
Date: Thu, 09 May 1991 21:20
Date: Thu, 09 May 1991 21:20
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1537 bytes
In article <168@titccy.cc.titech.ac.jp>, mohta@necom830.cc.titech.ac.jp (Masataka Ohta) writes: > ... > Agreed. The cost is not so small, but, anyway, for disk I/O, the processor > must transfer data between user buffer and buffer cache. It's far faster to fiddle with TLB's, PTE, MP-locks, and so forth than to copy a 4KByte page of words between kernel and user space. It's faster to copy a 4KB page of words than a 4KB page of bytes. There are numbers for the cost to byte swap during a word-copy on certain interesting RISC chips, and while they are not "prohibitive", they are "undesirable." Everyone by now has no doubt noticed the user-level instruction added to the 486 from the 386, the swap-the-bytes-in-a-32-bit-register instruction. INTEL added it despite the fact that you can swap bytes in place in likely registers in 4 instructions, each taking 2 clocks on a 386 or 1 on a 486. 4 instructions is a fraction of what is required elsewhere. Vernon Schryver, vjs@sgi.com
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!decwrl!sgi!vjs@rhyolite.wpd.sgi.com From: vjs@rhyolite.wpd.sgi.com (Vernon Schryver) Newsgroups: comp.arch Subject: Re: ACE (Was Re: Will NeXT survive? Grow with the times?) Message-ID: <102814@sgi.sgi.com> Date: 9 May 91 21:20:27 GMT References: <21199@cbmvax.commodore.com> <3005@spim.mips.COM> <168@titccy.cc.titech.ac.jp> Sender: guest@sgi.sgi.com Distribution: comp Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 21