🚀 go-pugleaf

In article <658@ctycal.UUCP> ingoldsb@ctycal.UUCP (Terry Ingoldsby) writes:

>...  One of the original features
>of RISC technology was the speed with which a design could be created
>and implemented.  Since the implementation technology has to be frozen
>at some point in the design cycle (I presume fairly early on) this
>means that performance of the implementation is inversely proportional
>to the time it took to produce it.  CISC machines take longer than
>RISC machines, so currently available CISC chips necessarily use older
>technology.

CISC system designers work with process designers.  Process designers generally
have some idea where they are going next.  Aggressivly designed CISC (or
RISC, for that matter) will be designed more-or-less in parallel with
the target process.  Pure in-house implementations can be even more
aggressive in that the two can have the end product as their common goal.

So there is no technical reason that a CISC chip released in Quarter X
should be any less "State of the Art" than a RISC chip released in Quarter X
with respect to technology (modulo the FABs).  If the CISC implementation
cycle is longer than the one for RISC then that means the CISC designers
have to peer a bit deeper into their process designers' minds but they can
also adjust to changes as they go.  And, if you watch closely, you will
sometimes see either flavor having a rev 1.0 release at X Mhz followed,
some months later, by an X++ MHz version 1.1 reflecting process and
implementation fine tuning (some do this the other way around - announcing
the X++ version, shipping "early" versions at X and then shipping the X++
version later).
-- 
Gary Bridgewater, Data General Corporation, Sunnyvale California
gary@sv.dg.com or {amdahl,aeras,amdcad}!dgcad!gary
"I am a pizza.  I am a pizza.  ..."