🚀 go-pugleaf

Subject: Re: Machines with cond. assignment instruction?

>Are there announced machines (specially micros) with
>some conditional assignment instruction.  I mean
>instruction such as the following:
>
>MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
>
>where, c1 refers to some result of some previous compare.
>
>Any pointers to such machines or any quantitative evaluation
>of usefulness of this instruction in the specific context
>of some machine would be appreciated.
>
>Thanks,
>Pradeep


     I believe that both DEC Alpha and (recent?) MIPS processors have 
instructions that work kind of like this.  

     MIPS uses it to minimize pipeline breakage (especially important 
on "superpiplined" implementations). 

     Alpha uses registers rather than condition code fields.  

     As I recall, on both MIPS and Alpha, either the target register is updated or is not updated (rather than being 
updated by one of two separate registers).  So it is not the exact 
instruction, but close ... the coding differences would seem 
inconsequential to me.

     My box full of information on processors is buried right now due to 
office remodelling, but for absolute answers about the processors mentioned, 
contact someone at SGI (nee MIPS ... John Mashey reads this newsgroup so I 
hope he'll correct me if I remember wrong).  I think I saw something posted 
by Dileep Bhandarkar recently, so he can set the Alpha story straight if I 
don't have it correct.