🚀 go-pugleaf

In article <AJC.93Jan4073719@thendara.pa.dec.com>, ajc@pa.dec.com (AJ
Casamento) wrote:
> 
>   You're right of course (must have been Holiday senility on my part). Having
> access to a common model (Verrilog, VHDL, or some such) for the ASIC would be
> a real plus. Actually, a bus transactor model would be a win as well. It would
> certainly tend to cut down on the issues of platform compatibility that seem
> to plauge a lot of the third party option world. Given a reasonably thorough
> model, there should be a lot less chance of having an option card work on one
> system platform and not on another one (I don't expect there to be any absolute
> solutions to this problem of course; I'm idealistic, not foolish ;-) and there
> are simply too many folks who will choose not to verify their designs).
> 
>   So add such a model to my list of items that should be supplied for this new
> interconnect.
> 
Gee, yet another opportunity to point out that the ANSI/IEEE Std 1596 SCI
Scalable Coherent Interconnect is just what you want!

The SCI spec is written in executable C code, and for building the SCI
interface chip you can buy Verilog from one vendor already, Dolphin SCI
Technology. Two chip houses have done this and expect to ship in a couple
months (Vitesse and LSI Logic), and some computer companies have done it
too and expect to make their own customized chips for their own internal
purposes.

The C code is in two levels. The low level specifies the handling of bits
and bytes to make packets, and the high level specifies some of the uses of
these packets. Some parts of each might correspond to your "bus transactor
model."

But of course I understand that this discussion is futile--any engineer
worth his salt (salary) gets his only pleasure in life from designing his
own new unique solution to this problem! ;-)  Sigh.  But maybe his
competitors will have higher profits because they get the benefit of the
support infrastructure that grows around standards.

--------------------------------------------------------------
-- David B. Gustavson, Computation Research Group, SLAC, POB 4349 MS 88,
    Stanford, CA 94309   tel (415)961-3539  fax (415)961-3530
-- What the world needs next is a Scalable Coherent Interface!
-- Any opinions expressed are mine and not necessarily those
   of the Stanford Linear Accelerator Center, the University, or the DOE.