🚀 go-pugleaf

In article <1993Jan8.111731.19116@odin.diku.dk>, torbenm@diku.dk (Torben
AEgidius Mogensen) wrote:
> 
> Newer processors (including the new ARMs) tend to have selectable
> endianness instead of byte swap instructions.
> 
That's too bad, because selectable endianness isn't well defined and won't
solve the problem in general. The trouble becomes obvious when you consider
general interconnected systems with multiple bridges connecting data paths
of various widths. Unless these bridges agree to preserve the relative byte
addresses of all data, it gets thoroughly shuffled as it propagates from
one convention to another. 

Thus the principle of Address Invariance has (after many person-years of
arguments) been adopted by the IEEE bus standards (like 1596 SCI and 896
FutureBus+). One of the SCI follow-on standards addresses the final part of
this problem, P1596.5 Data Transfer Formats. The idea is to give the
compiler enough information so that it can unscramble the data in a
heterogeneous environment, generating only those swaps that are needed.
Efficient swap instructions work well for this, but selectable endianness
doesn't hack it.
Contact the P1596.5 chair for more info, David James: dvj@apple.com.

By the way, the clearest definition of endianness that I know is:

In a Big-endian machine, the significance of bytes (or bits) in any data
item decreases as the address (byte or bit number) increases.

In a Little-endian machine, the significance of bytes (or bits) in any data
item except character strings increases as the address (byte or bit number
increases. For character strings the significance decreases.


Numbering bits and bytes oppositely is a loser, as Motorola discovered when
they added the Bit Field instructions in the 68020. They are not
independent choices once instructions exist that couple them. 

Endianness describes how data gets loaded into registers, not how it gets
mapped to bus lines or other hardware. For multiplexed buses, an additional
descriptor is needed, which distinguishes "Big addressan" and "Little
addressan" sexes. (Ugh, but that's the term that won out.) The existence of
this independent choice confuses the endianness arguments considerably, and
was a major cause of the confusion that caused selectable endianness to be
implemented incorrectly in some processors. 

--------------------------------------------------------------
-- David B. Gustavson, Computation Research Group, SLAC, POB 4349 MS 88,
    Stanford, CA 94309   tel (415)961-3539  fax (415)961-3530
-- What the world needs next is a Scalable Coherent Interface!
-- Any opinions expressed are mine and not necessarily those
   of the Stanford Linear Accelerator Center, the University, or the DOE.