🚀 go-pugleaf

I was cruising through my WE32100 chip set data sheets and noticed the
WE32103 DRAM Controller. The sales sheet looked interesting so I started
going through my data sheet that went with it. At least according to the
data sheets, it looks pretty good.

It drives up to 88 devices and drives the 1M-bit rams. It supports 1-byte,
2-byte, 3-byte, word, double-word, and quad-word memory access. It has
support for page and nibble-mode rams. An internal refresh counter and
timer help simplify refresh. It has a synchronous AND asynchronous bus
interface which make it easy to drop on a 68000-type system. It even has
the capability of "pretranslation" in which it will strobe the low order
bits of a page on the row address in anticipation of a memory access. If
the chip is not selected, it then aborts the access before any harm is done.
This is to allow an MMU to translate the upper addresses while you are
starting your memory access and give you a little more breathing room.

This looks like a great chip to couple with a 68030 and 64 1Mbit chips for
a small, fast system. Does anyone know if real silicon exists for this thing
or was it announced ahead of time? Also, the "pretranslation" looks like it
falls under the Sun-Microsystems patent for strobing the low order address
bits on the rams before the high order to get more time in memory management
translation. Any problems with that?

Other information... single 5-volt supply. Comes in a 125-pin PGA (Pin Grid
Array). It pulls a maximum of 1.3W on the fastest chip (18MHz). The address
outputs are rated at 450pF.

	Enjoy,
-- 
Jeff Lee
CSNet:	Jeff @ GATech		ARPA:	Jeff%GATech.CSNet @ CSNet-Relay.ARPA
uucp:	...!{akgua,allegra,hplabs,ihnp4,linus,seismo,ulysses}!gatech!jeff