🚀 go-pugleaf

Let's assume that the RISC and CISC machines under consideration are
identical except for instruction encoding; the CISC being microcoded and
each RISC instruction corresponding to one micro instruction.

CISC compilers tend to pack as many operations together in single
instructions as they possibly can, but this implies a certain amount of
redundancy because the complex instructions represent general case sequences
of micro instructions.  Initially, there will be several RISC instructions
for each of the CISC instructions, perhaps 3:1.  However, many of them will
be optimized away.

This is because the RISC compiler can recognize and remove redundancies in
the CISC micro instruction sequences.  Generally, RISC implies more available
expressions, which makes value propagation and common subexpression
elimination more productive.  Taking arbitrary basic blocks of RISC code and
doing rather simple analysis, we have often found that only about 1/4 of the
operations remain after optimization...  this is a very unlikely scenario
for CISC operations.

In summary, redundant "micro instructions" of the CISC operations nearly all
disappear from the optimized RISC code, hence a 1:1 ratio of RISC:CISC is
quite possible.  How do you get better than 1:1?  The only way is if some
entire CISC instructions are useless; i.e., you can't do better than 1:1
unless the RISC compiler is "smarter" than the CISC compiler.

								-hankd

PS: If the above sounds like "why nobody should ever build a CISC," let me
    remind folks that we're assuming instruction bandwidth isn't an issue
    and the code you care about really has such low-level redundancies.  Of
    course, finer-grain (RISC) compiler control can require more instruction
    bits per computation, so there's still plenty to argue about. ;-)