🚀 go-pugleaf

From article <2203@taux01.UUCP>, by cjosta@tasu77.UUCP (Jonathan Sweedler):
> [...]                                      I was always under the
> impression that RISC machines need more complex compilers, not just
> because of the need for more optimization, but because RISC chips are
> 'dumber' than CISC chips.  i.e. a lot of the complexity of the chip is
> moved to the software.

You are confusing complexity with quantity.  RISC compilers usually
(but not always) generate more instructions for a given task than
CISC compilers do.  However, the task of generating code for RISC
is _much_ easier than generating code for CISC.  So, the RISC compiler
is simpler than the CISC compiler even if it does produce more output.


> [...]                   Don't forget that MIPS, one of the early RISC
> chips, stands for 'Microprocessor without Interlocked Pipe Stages.'
> This means that interlocks must be handled in the compiler.  So
> forgetting about all optimization, just writing a compiler that WORKS
> on a RISC chip is by DEFINITION harder than writing a compiler for a
> CISC chip.

You stated that incorrectly.  Forgetting about all optimization, just
writing a compiler that WORKS on a non-interlocked chip is by DEFINITION
harder than writing a compiler for an interlocked chip.  This doesn't
necessarily have anything to do with RISC vs. CISC.

[...]
> Just so I don't start a new war here, I'm not saying any of this is
> bad.  RISC seems to be proving its point.  But I think that a RISC
> compiler is NECESSARILY more complex than a CISC compiler, regardless
> of the level of optimization performed by the compiler.

The strange fact is: for a given degree of optimization, it is harder
to compile for CISC than RISC.  This is hardly surprising.  Computers
are real good at simple repetitive tasks (like generating code for
RISC machines).  Complex tasks (liking making good use of a rich
instruction set on a CISC) require more effort on the part of the
_programmer_.