🚀 go-pugleaf

cjosta@tasu77.UUCP (Jonathan Sweedler)
> Don't forget that MIPS, one of the early RISC
> chips, stands for 'Microprocessor without Interlocked Pipe Stages.'
> This means that interlocks must be handled in the compiler.  So
> forgetting about all optimization, just writing a compiler that WORKS
> on a RISC chip is by DEFINITION harder than writing a compiler for a
> CISC chip.

Actually, this is usually handled by a recoding assembler.  You 
don't really want to handle it in your compiler unless your compiler 
integrates the assembly phase and emits .o files directly.  The reason 
is that you have to do some analysis on the whole program when you 
are finished to try to fill the delayed branch slots, and to reorder 
instructions, inserting no-ops where necessary, to avoid pipeline 
conflicts.  So you might as well do it then.

And writing a RISC compiler isn't `by DEFINITION'' harder: you just
pad out everything with no-ops (both delayed branch slots and the 
actual instructions to insure that the pipeline flushes.)  Pretty 
poor object code, but you don't have to do any analysis at all.

Writing a compiler that makes use of the non-trivial features of a 
machine, RISC or CISC, is very tricky.  For instance, I still haven't
found out how I can generate code to use those all those nice BCD 
instructions in my 68k.....


Jonathan A. Chandross
Internet: jac@paul.rutgers.edu
UUCP: rutgers!paul.rutgers.edu!jac