🚀 go-pugleaf

In article <42942@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
....
>>Correct me if I'm wrong, but I remember looking at some of the initial
>>specs for the Intel 860 and that thing looked like a nightmare to write
>>a compiler for.  Forget about optimizations, just getting floating
>>point results out of the FP pipeline, requires that the compiler have
>>knowledge of the internals of the hardware.

>This is true, and makes me believe that IEEE FP and RISC are
>incompatible.  Both major implementations (860 and 88000 (I'm glad I
>can admit knowlege of the 88000 now)) show that this force-fit causes
>problems.  By RISC arguments, let sw handle the exceptions.  But IEEE
>FP has so many exceptions by its over-complex nature that [not the
>compiler really, the OS] absolutely must be able to handle said
>hardware internals, and must do it efficiently; underflow happens
>more often than you think.

This seems to be an over-generalization.
Maybe this means that 860s and 88000s have problems (beyond whether or
not these are the 2 "major" implementations :-).  I assume these refer to
the issues of dealing with imprecise exceptions, which is certainly
possible, if complicated, or extremely complicated.  Anyway, please explain
more why IEEE FP and RISC are incompatible, as the RISCs that are
already out there in systems manage to deal with it....
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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