Article View: comp.arch
Article #1617Re: RISC is NOT micro-code (was Re: Compiling - RISC vs. CISC
From: Sean Fagan
Date: Fri, 21 Jul 1989 00:18
Date: Fri, 21 Jul 1989 00:18
47 lines
2772 bytes
2772 bytes
In article <BRUCE.89Jul18181114@heather.pooh.com> bruce@heather.pooh.com (Bruce Robertson) writes: >Shouldn't all these optimizations be done in the machine independent >portion of the compiler? Yes, all of the optimizations you mentioned (which I deleted) *should* be done in the mi part of the compiler. For compilers which are intended to support multiple architectures (remember, not all are), it usually is. >A well designed compiler should have >all the machine dependencies isolated in one relatively small module >(relative to the size of the entire compiler). RISCy things like delay >slot filling are easiest to handle in the assembler, or other post >processor. Except that delay-slot filling is not the only type of optimization that exists. For some machine (such as a CDC Cyber), doing certain instructions after another would slow it down, while on other machines, it can speed up. Specifically: memory accesses and various register combinations. Some microprocessors can be optimized to do certain kinds of memory fetches faster, while the Cyber does sequential accesses best. Also, something like: FX6 X5*X3 FX7 X6/X1 is bad practice on a cyber (put other instructions in between). On some other machines (specifically VLIW and the ilk), that could be reduced to a pseudo-one instruction which did: X6 <- X5*X3, X7 <- <multiply unit> / X1 which would execute in parallel as much as possible (I know, I know, that's really a bad example. I had some better code than that lying around, but I forget where I put it). Then there's the choice of instruction selection. Sometimes, which instructions you choose can change some of your "machine independent" optimizations. Also, you have to choose registers properly (is it better to put array addresses into registers, or would it be better to put other variables in registers and let the hardware compute the array address? For something like a '486, this could be a tough choice...). In other words, life isn't as simple as we would like it to be... -- Sean Eric Fagan | "Uhm, excuse me..." seanf@sco.UUCP | -- James T. Kirk (William Shatner), ST V: TFF (408) 458-1422 | Any opinions expressed are my own, not my employers'.
Technical Details
Message-ID:
<3070@scolex.sco.COM>Path:
arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!sco!seanfReferences:
<389@h> <2700017@prisma> <754@biar.UUCP> <BRUCE.89Jul18181114@heather.pooh.com>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!sco!seanf From: seanf@sco.COM (Sean Fagan) Newsgroups: comp.arch Subject: Re: RISC is NOT micro-code (was Re: Compiling - RISC vs. CISC Message-ID: <3070@scolex.sco.COM> Date: 21 Jul 89 00:18:11 GMT References: <389@h> <2700017@prisma> <754@biar.UUCP> <BRUCE.89Jul18181114@heather.pooh.com> Reply-To: seanf@scolex.UUCP (Sean Fagan) Organization: The Santa Cruz Operation, Inc. Lines: 47