🚀 go-pugleaf

In article <1989Jul19.165456.20210@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes:
> Things like software pipe interlocks, delayed branches, etc. can almost
> always be deferred to a cleanup pass that is very stupid and simple.  (On
> some RISC chips, this sort of thing is done in the assembler, not the
> compiler at all.)  One of the surprises that came out of RISC work is
> that moving some of these things into the software really costs very
> little.  You may occasionally miss an optimization opportunity by not
> having the earlier passes aware of the final rearrangement, but it's
> not really very frequent.

The early RISC compiler work (e.g., Gross) seems have suggested this, but
later work (e.g., Bird's thesis from U. Michigan) has shown that doing
register allocation before instruction scheduling will often cause code
quality to be much poorer.

The register allocator generally wants to do all of one computation, then
all of the next, etc. to minimize the number of concurrently live variables.
The instruction scheduler generally wants to interleave "unrelated"
compuations to minimize the effects of memory latency and such.  This issue
came up when we were considering instruction scheduling for our 88000 Scheme
compiler.  (See our paper in the ASPLOS-III proceedings).

What happens in practice when register allocation is done first, is that the
register assignments introduce a lot of artificial constraints on the
scheduler, causing it to do a much poorer job.  In other words, the
assignment of common registers to computations that could otherwise be
interleaved  makes such interleaving impossible.

		Steve Vegdahl
		Computer Research Lab
		Tektronix Labs
		Beaverton, Oregon