🚀 go-pugleaf

In article <13995@lanl.gov>, jlg@lanl.gov (Jim Giles) writes:
> (A)   Instruction selection
 ...
> (B)   Register allocation
 ...
> (C)   Code ordering
 ...
> Any one of the above is fairly easy to do in isolation.  Any two of the
> above are difficult to do because they interfere with each other.  Only
> CISC archetectures even have to consider (A) since, in a RISC, this
> step is _very_ simple.  I claim that CISC compilers must do all three
> of the above in order to be competitive.  Hence, my claim that CISC is
> harder to compile for than RISC.

On the other hand, (C) is generally much more difficult for a RISC
architcture, due to architectural features such as delayed branches and
exposed memory latency.  These features tend not pose difficult problems
when treated in isolation---as was done in the early RISC compiler work---but
cause additional compications when combined with other phases.

I think that the RISC vs. CISC compiler issue is more or less a toss-up.
With either type of architecture, you can write a *simple* compiler by
compiling:
  * to a RISC subset
  * without code organization
For higher quality code, CISC compilers are complicated by the need to
consider complex addressing modes, while RISC compilers are complicated
by the need to consider delayed branches and memory latency.  Both kinds
of complications have interdependencies with other aspects of optimization.

		Steve Vegdahl
		Computer Research Lab
		Tektronix Labs
		Beaverton, Oregon