🚀 go-pugleaf

In article <3256@wpi.wpi.edu> jhallen@wpi.wpi.edu (Joseph H Allen) writes:


   A question for those old diehard dec fans...  We (WPI) used to have
   a DECSYSTEM 20.  One interesting thing about the DEC 20 (and I
   guess DEC 10 and pdp-6 as well) is that the registers are the first
   8 or 16 locations in the main memory map.  Does anyone know if code
   can be run in the registers?  And if so, does it execute any faster
   than if it was in normal memory?

YES, it was common practice for very small tight loops to use 'blt'
(block transfer) to put a few instructions into the registers and then
transfer control to them. Yes it sped things up. I once did this as
a hack to get the most performance out of a GCD routine for some
rational arithmetic and it was found in a lot of other pieces of
software.

From "The Evolution of the DECsystem 10", CACM V21 n1, Jan 1978:
C. G. Bell, A. Kotok, T. N. Hastings, R. Hill. Copyright 1977
Association for computing Machinery. Permission is granted to
republish, but not for profit, all or part of the material provided
that ACM's copyright notice is given, ... see the magazine for the
rest...

(Also printed, I believe in "Computer Engineering, a DEC view of
hardware system design" Digital Press, 1978. The book prohibits copying,
so I am including this from the CACM article rather than the identical
text in the book :-)

"Since the ACs were in the address space, ordinary memory could be used
in lieu of fast registers to reduce the minimal machine price. In
reality, nearly all users bought fast registers."

   Here's some other interesting DEC 20 features for those who don't know:

         ...

	   - The family of computers which the DEC 20 was based didn't
	   originally use a stack.  There are a bunch of instructions
	   which allow subroutine calls to occure with linked lists
	   instead of stacks.

I believe that even the PDP-6 had stacks built in from the beginning.
From the same paper as above: (discussing original design issues)

"A stack machine was considered, based on B5000 and ...
The compromise we made was to provide a number of instructions to operate
on a stack, yet use the general registers as stack pointers."
...
"A general register architecture was selected with the registers in the memory
address space."

	   - The DEC 20 didn't really have CC bits and all
	   instructions were 1 word long so the O.S. (Tops-20 aka.
	   Twenex) indicated different return conditions from O.S.
	   calls by returning at different places.  So an error return
	   might be the next instruction after the O.S. call and a
	   success condition would be 2 at 2 instructions after the
	   O.S.  call.

The 1 word instructions allowed extensive use of "test-and-skip"
style branching. I recall that I thought the condition codes of the
360s and the PDP-11 when it came along to be very inelegant.

It might provide fertile noise (or is that signal?) for this newsgroup
to consider the tradeoffs in a "test and skip next instruction" vs
the more common (today) "Branch based on previous instruction's CC" in
an today's architectural climate.

					Skip Egdorf
					hwe@lanl.gov