🚀 go-pugleaf

In article <1451@mdbs.UUCP> wsmith@mdbs.UUCP (Bill Smith) writes:
>In article <23379@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
>> In article <337@venus.iotek.UUCP> garyb@iotek.UUCP (Gary R. Burrell) writes:
>> 
>> >IEEE Micro December 1988
>> >
>> >	A Special Issue on DSP processors, contains detailed articles
>> >on the TMS320C30, DSP32c and DSP96002.  These are fairly good articles
>> >about the various DSP processors.  The only part of the issue I really
>> >question is the editors afterword in which they come up with some
>> >amazing figures for Linpack ratings of the TMS320C30 (20 MFLOPS) and
>> >DSP96000 (30 MFLOPS).  I question these ratings as most supercomputers
>> >only get about 1/10 of there peak performance rating on the LINPACK
>> >benchmark.  
>
>> I conjecture that what they must mean is the inner-loop timing for
>> the standard LINPACK code, but with zero-wait-state memory,
>> ..... Continued but deleated


>Sorry this is so late a followup.  
>
>I haven't seen the article under discussion nor information about the
>DSP chips except the TMS320C30, and that information may invalidates John
>Mashey's comments.   The TMS320C30 has a fairly large amount of program 
>space on chip (something like 4k words) that is zero-wait state and probably
>also multi-ported (but I might be getting the register file confused with
>the memory buffers). 
>
>If the inner loops fit within the on-chip memory or can be paged in and out
>with the on-chip DMA logic, the TMS320C30 can do some pretty amazing things.
>The other chips may also have similarly sophisticated architectures, but
>I'm not sure.  (In case you can't tell, I like the TMS320x0 chips.)
>
>Don't incriminate a vendor about flakey benchmark numbers without verifying 
>that the benchmarks are in fact flakey (which I haven't actually done, but...)
>
>Bill Smith
>pur-ee!mdbs!wsmith  (A long time ago in a universe far far away, I was 
>			wsmith@cs.uiuc.edu, but no longer :-)

Just to Clarify Things I wasn't trying to incriminate the vender about
flakey benchmarks.  What I was questioning was an article which
compared benchmark data (On SuperComputers) to estimated Linpack
ratings on DSP's.  There was no benchmark done (As far as I could
tell).  This violates one of the Cardinal Rools of Benchmarking in
that Simulated, Estimated, and Actual Benchmark data should not be
compared.


	I like the TMSC320C30 and while it is an impresive chip
capable of impresive performance and has a peak speed of 33.3 MFLOPS
(This is manufactures data), It should be clarified that these
performance values are only available by using the
Multiply-and-Accumulate cycle and only while operating out of internal
memory.  The processor only :-) has a rated speed of 16.7 MIPS and
accesses to external memory can cause a high performance penalty.
Because of these facts and others I questioned the validity of the
estimated benchmarks.  I could be wrong to do this, I have been know
to be wrong before. :-(  I would be very interested in seeing actual
benchmark data for the Linpack benchmark run on a real TMS320C30 (Any
one from TI out there :-) ), and if it actually get 20 MFLOPS S.P.
Linpack I will be the first one to jump on the bandwagon and shoot
down my previous comments.

			Gary R. Burrell

Disclamer:  I have nothing to do with TI, AT&T, Motorala ETC. and have
nothing to gain by questioning these Benchmarks, other than clarifying
the facts.  I Like the TMS320 family and must state that any DSP selection
should be judged on how well a particular chip performs for that
application not how well it performs on the XYZ Benchmark. 

			<<<<<<******>>>>>>
Gary R. Burrell, Iotek Inc,     |*| E-Mail: garyb@iotek.uucp	|*| 
1127 Barrington St., Suite 100, |*| Fax:    (902)420-0674	|*|   
Halifax, N.S., B3H 2P8, Canada  |*| Phone:  (902)420-1890	|*| 

Damm it Jim 
  I'm a Doctor not a Computer Scientist!
              
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