🚀 go-pugleaf

In article <3024@alliant.Alliant.COM> jeff@alliant.Alliant.COM (Jeff Collins) writes:
>	Which policies are these?  How does one share memory in a
>	multiprocessor when you can't have external bus watchers?
>	Actually never mind that, how do you switch a process from one
>	processor to another (I don't count flushing the D-cache on
>	each context switch as a viable answer)?

Although you don't count flushing the D-cache as a viable answer, for
large scalable multiprocessor systems such a solution is indeed viable.
In particular, if you are not talking about a bus architecture at all
where snooing is not very easy to do,  write-through caches which
use the volatile keyword in C as a mechanism to force a cache miss
on a read are quite useful.  Non-bus systems don't have a memory
bandwidth problem, they generally have a memory latency problem.
The write-through cache can be tolerated because the needed bandwidth
is available and the cache flush is quick because cache lines only
need to be forgotten, not written to memory.  A single instruction
could nail the whole cache.

This is of course somewhat of a tangent to the issue for the i860.
The i860's cache is not write-through with explicit user code
management of the cache lines so it does not fit in the "non-bus"
scheme mentioned above very well, and the current on chip cache
does not have a coherence strategy useful for bus based shared
memory multiprocessors (other than to keep shared data out of the
on chip cache).  For such a small on chip cache the "flush
the cache on a context switch" is not really much of an issue. I
suspect that you have to do this anyway for a single cpu machine
as the cache is a virtual memory cache.



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