🚀 go-pugleaf

In article <1562@vicom.COM> hal@vicom.COM (Hal Hardenbergh (236)) writes:
>Uh, what did you think of Nick Tredennick's assessment of RISC in the Feb issue
>of Microcomputer Report?  Was that the _second_ most inaccurate assessment of
>RISC that you have yet read?

I found his article to be more an accurate assessment of microprocessor
trends in general.  I just KNEW his article would get mentioned here
sooner or later.  A lot of the stuff he said needed to be said
eventually.

RISC is indeed a technology window, driven largely by the amount of
stuff you can fit in a chip.  Look at what is being added now that you
can fit more than a simple CPU core in a chip:

   Floating Point
   29000 null-terminated-string handling instructions
   Choice of endian-ness
   Caches; in fact with extremely complex, multi-mode capabilities
   Fully associative address translation caches
   Harvard architecture
   Multiprocessor capability

The trend in computer evolution is truly toward greater hardware
complexity.  This has been demonstrated countless times.  The
reversion back to too much simplicity did happen in the late 70's, but
here we are again, back on the same curve.

There is a true need for complexity.  How many times when reading this
newsgroup do you see things like, "Yes but that chip doesn't have <my
favorite feature>" where the feature is anywhere from instruction
cache size to multiprocessor cache invalidation (see N-10 bashing)?
Hardly a RISC headset!

Pure RISC religion is to keep things as simple as possible in order to
make the cycle time as fast as possible.  This can only go so far;
real memories must be used, the chip must be interfaces to with real
hardware, etc.  Clearly, the way to get past this brick wall is to do
more in parallel, either with more powerful instructions (including
VLIW/compiler technology), and/or multiprocessing.

Companies must make money.  They will do this by making not tiny
low-cost RISC micros, but the most complex thing they can fit in a
chip.  They need this so they can get product differentiation and thus
better margins.  The million transistors will NOT be used entirely for
large caches, but for more instructions, addressing modes, faster
floating point, elegant exception handling, etc.  And, just watch,
they will still find a way to call them RISC's!

I predict that the next hardware features to come back will be
auto-increment addressing and the hardware handling of unaligned data.

I am not saying that RISC is bad, but it was an interesting exercise
from which we all learned a lot.
:-) Stan