🚀 go-pugleaf

About physical i-caches: it is not clear to me that a context switch
may not render lines in even physical i-caches invalid.  In a processor
where the i-fetch unit is what fills the i-cache, there is a chance
that after a context switch the OS will map a different page (of
instructions, perhaps) into a physical page frame that has some lines
in the i-cache.  The pager usually updates (or its data is run through)
the d-cache; hence, these updates won't get to the i-cache.

I see three ways around this: have the pager flush the i-cache
(selectively or always), use a hardware pid with the (*physical*)
i-cache, or somehow run paging of instruction pages through the i-cache.

Most of the arguments against always-flushing the i-cache are irrelevant
anyway since modern on-chip i-caches are too small to preserve any lines
of processes between context switches.

------
Tom Conte      Computer Systems Group, Coordinated Science Lab
               University of Illinois, Urbana-Champaign, Illinois
...The opinions expressed are my own, of course.
uucp:	 ...!uiucdcs!uicsrd!conte    internet:	conte@bach.csg.uiuc.edu