🚀 go-pugleaf

In article <3830004@hpcuhb.HP.COM> gupta@hpcuhb.HP.COM (Mayank Gupta) writes:
>
>>Are there any micros or chipsets out there that support an address space
>>larger than 32 bits?  The current trend in micros seems to be toward 64-bit
>>data paths but only 32-bit address paths.  In a large-scale parallel
>>processor, this starts to feel a bit like a PDP-11.

>It was gonna come around sooner or later.  HP saw this coming five years ago
>when we developed our HP-PA (Precision arcitecture "RISC").  This gives you:
>
>32 bit virtual and 32 bit physical addressing : Level 0 compliance.
>48 bit virtual and 32 bit physical addressing : Level 1 compliance.
>64 bit virtual and 32 bit physical addressing : Level 2 compliance.
>
>with a very comprehensive memory management system, including levels (> 2) of
>protection.
>
>HP has been shipping 64 bit virtual address machines.  All of the above are
>32-bit integer and IEEE compliant floating point machines.

1) can you say more about what this "Level x compliance" means?
	(Does that mean that you can build HP PA machines with 32/32, and that's	called Level 0?  or does it mean something other than compliance with
	an HP-internal spec?)

2) I suspect that the original question was looking for machines more like
some supercomputers, i.e., with 64-bit integers and addresses that are
used directly as such (which I don't think HP PA does: correct me if I'm
wrong, but aren't there segment registers that can be controlled by the
compilers, rather than 64-bit flat addresses?)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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