Re: Bandwidth and RISC vs. CISC

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Article #21050

#21050

From: Peter da Silva
Date: Thu, 04 May 1989 13:08

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In article <10544@cit-vax.Caltech.Edu>, yair@tybalt.caltech.edu (Yair Zadik) writes:
> A couple of years ago there was an article in Byte about a proposed design
> which they called WISC for Writeable Instruction Set Computer.
> ...each compiler could optimize the instruction set for its language.

Sounds like a great idea for an embedded controller, but can you imagine what
context switches would be like in a general purpose environment with multiple
supported compilers...?
-- 
Peter da Silva, Xenix Support, Ferranti International Controls Corporation.

Business: uunet.uu.net!ficc!peter, peter@ficc.uu.net, +1 713 274 5180.
Personal: ...!texbell!sugar!peter, peter@sugar.hackercorp.com.

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!ficc!peter

References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <10544@cit-vax.Caltech.Edu>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!ficc!peter
From: peter@ficc.uu.net (Peter da Silva)
Newsgroups: comp.arch
Subject: Re: Bandwidth and RISC vs. CISC
Message-ID: <4074@ficc.uu.net>
Date: 4 May 89 13:08:23 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <10544@cit-vax.Caltech.Edu>
Organization: Xenix Support
Lines: 13

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