🚀 go-pugleaf

In article <10544@cit-vax.Caltech.Edu>, yair@tybalt.caltech.edu (Yair Zadik) writes:
> In article <231@celit.UUCP> dave@celerity.UUCP (Dave Smith) writes:
> >	The problem I have with RISC designs are that they use up too much
> >memory bandwidth.
> A couple of years ago there was an article in Byte about a proposed design
> which they called WISC for Writeable Instruction Set Computer.
> I haven't heard else about it.  Is anyone out there working on such a 
> processor or is it just a bad idea?
A couple of years ago Phil Koopman took his WISC stuff to Harris - I think
their working with it.  He had a 32bit CPU built from off-the-shelf TTL
logic that plugged into an IBM PC and ran at 10Mhz.  It was stack based, 
Harvard archecture and a completly writable micro-code store.  He had some
amazing throughput numbers on it, and had tweaked micro-code for Prolog, C
and some other stuff (Lisp?).  Anyhow Harris is supposed to be putting
together a chip from it.

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