🚀 go-pugleaf

John Mashey says:
>(OPINION) one must also
>assume that DG's claim of 100-mips ECL 88K's in 1991 is sandbagging:
>CMOS/BiCMOS chips will be banging around near that performance level
>that year also, so ECL should either be earlier or faster....

  DG is typically VERY conservative about schedules and performance estimates....
This is in stark contrast to most of the chip vendors (Intel is a major
culprit here) who announce "available now" when they mean "we have built 
a few and they kinda work", and "clock frequencies of N Mhz (where N is
large)" when they really mean "it works at room temperature at N Mhz, if
you have 5ns zero wait state RAMs".

  As an example:

  I took a look at the Intel i860 Processor Performance brief (Release 1.0),
and it quotes 40Mhz CPUs (although their benchmark system is only 33Mhz),
and at that frequency they quote ZERO WAIT STATE MEMORY, and BUGFREE silicon!

Intel's Linpack numbers are not even on real hardware.  They are simulated,
using assembly coded BLAs, and they assume that all the y[i] reside in the
cache.  The BLAs are written unrolled (4 results per 17 clocks).  And they say
"The projected performance takes into account future improvements in the
vectorizer, compilers, and vector libraries."

In my experience:

  MIPS is a LOT better at providing real numbers, and Sun is better than Intel
(although I understand that their claims for the Sparcstation are still more
like PEAK numbers than sustained numbers.  Anybody have any REAL data?).

  My preference is to have a third party do the numbers (no fudging allowed!).
Look for an upcoming issue of MIPS magazine for a relatively unbiased set of
numbers on our AViiON ($7995) workstation.

  Anybody know how the SPEC group is doing (John Mashey?)?   

Mike Pogue
Data General Corp.
Westboro, MA.

These are my opinions, nobody elses....